2025 (Current Year) Faculty Courses School of Computing Department of Computer Science Graduate major in Computer Science
Computer Organization and Architecture
- Academic unit or major
- Graduate major in Computer Science
- Instructor(s)
- Kenji Kise
- Class Format
- Lecture (Face-to-face)
- Media-enhanced courses
- -
- Day of week/Period
(Classrooms) - 5-6 Thu (M-112(H117))
- Class
- -
- Course Code
- CSC.T440
- Number of credits
- 100
- Course offered
- 2025
- Offered quarter
- 4Q
- Syllabus updated
- Sep 29, 2025
- Language
- English
Syllabus
Course overview and goals
This course aims to provide students with cutting-edge technologies and future trends in computer architecture, with a focus on the microprocessor, which plays a crucial role in the downsizing, personalization, and improvement of performance and power consumption in computer systems such as PCs, personal mobile devices, and embedded systems.
In this course, students will first learn about instruction set architectures and mechanisms for extracting instruction-level parallelism used in out-of-order superscalar processors. After that, students will learn mechanisms for exploiting thread level parallelism adopted in multi-processors and multi-core processors.
Course description and aims
By taking this course, students will learn:
(1) Organization and architecture for today's high-performance processors
(2) Mechanisms for extracting instruction level parallelism used in high-performance microprocessors
(3) Methods for exploiting thread level parallelism adopted in multi-processors and multi-core processors
Keywords
Computer Organization, Computer Architecture, RISC-V, Instruction Level Parallelism, Thread Level Parallelism, Multi-processors, Multi-core Processors, Memory Consistency Model, Interconnection Network
Competencies
- Specialist skills
- Intercultural skills
- Communication skills
- Critical thinking skills
- Practical and/or problem-solving skills
Class flow
Before coming to class, students should read the course schedule and check what topics will be covered. Required learning should be completed outside of the classroom for preparation and review purposes.
Course schedule/Objectives
| Course schedule | Objectives | |
|---|---|---|
| Class 1 | Computer Organization and Architecture |
Understand the basics of the computer system, pipelining, instruction level parallelism, and multi-core processors |
| Class 2 | Instruction Level Parallelism: Memory System, Instruction Fetch, and Branch Prediction |
Understand the organization of memory systems, instruction fetch, and branch predictions to exploit instruction level parallelism |
| Class 3 | Instruction Level Parallelism: Register Renaming and Dynamic Scheduling |
Understand the register renaming and the dynamic scheduling to exploit instruction level parallelism |
| Class 4 | Instruction Level Parallelism: Multiple Issue, Speculation, and Out-of-order Execution |
Understand the multiple issue mechanism, speculation, and out-of-order execution to exploit instruction level parallelism |
| Class 5 | Thread Level Parallelism: Coherence and Synchronization |
Understand the coherence and synchronization for thread level parallelism |
| Class 6 | Thread Level Parallelism: Memory Consistency Model |
Understand the memory consistency model for thread level parallelism |
| Class 7 | Thread Level Parallelism: Interconnection Network and Many-core Processors |
Understand the interconnection network and many-core processors for thread level parallelism |
Study advice (preparation and review)
To enhance effective learning, students are encouraged to spend approximately 100 minutes preparing for class and another 100 minutes reviewing class content afterwards (including assignments) for each class.
They should do so by referring to textbooks and other course material.
Textbook(s)
John L. Hennessy, David A. Patterson, Christos Kozyrakis. Computer Architecture A Quantitative Approach, 7th Edition. Morgan Kaufmann Publishers Inc., 2025
Reference books, course materials, etc.
William James Dally, Brian Patrick Towles. Principles and Practices of Interconnection Networks. Morgan Kaufman Publishers Inc., 2004.
Evaluation methods and criteria
Students will be assessed on their understanding of computer architectures that utilize instruction-level parallelism and thread-level parallelism.
Students' course scores are based on the final report (60%) and assignments (40%).
Related courses
- CSC.T363 ： Computer Architecture
- CSC.T341 ： Computer Logic Design
Prerequisites
Students who have already earned credit for CSC.T433 Advanced Computer Architecture are not eligible to take this course.
Enrollment in the related courses is desirable.
Contact information (e-mail and phone) Notice : Please replace from ”[at]” to ”@”(half-width character).
Kenji Kise: kise[at]comp.isct.ac.jp
Office hours
Contact by e-mail in advance to schedule an appointment.