2025 (Current Year) Faculty Courses School of Computing Undergraduate major in Computer Science
Computer Architecture
- Academic unit or major
- Undergraduate major in Computer Science
- Instructor(s)
- Kenji Kise / Nesrine Berjab
- Class Format
- Lecture/Exercise (Face-to-face)
- Media-enhanced courses
- -
- Day of week/Period
(Classrooms) - 5-8 Tue (情報工学系計算機室) / 5-6 Fri (情報工学系計算機室)
- Class
- -
- Course Code
- CSC.T363
- Number of credits
- 210
- Course offered
- 2025
- Offered quarter
- 3Q
- Syllabus updated
- Sep 29, 2025
- Language
- Japanese
Syllabus
Course overview and goals
In the computer science area, it is important to understand the basic structure of computer systems and architectures for high-performance computers learning the interface between hardware and software. This course teaches the role and principles of key components for computer systems such as processors, memory technologies, input/output, multiprocessors, and multicore.
In the exercise, students describe the computer systems including a processor and caches in hardware description language such as Verilog HDL, and verify their operation by the simulation and implement them on the hardware board with an FPGA,
and learn the interface between hardware and software.
Course description and aims
At the end of this course, students will understand
- Understand the basic structure of computer systems and architectures for high-performance computers,
- Understand the role and principles of components for computer systems such as processors, memory technologies, input/output, multiprocessors, and multicore,
- Obtain skills for designing typical computer systems with a hardware description language.
Keywords
Computer Architecture, Processor, Superscalar, Cache, Memory Hierarchy, Virtual Memory, Multiprocessors, Multicore, Hardware Description Language, Verilog HDL, FPGA
Competencies
- Specialist skills
- Intercultural skills
- Communication skills
- Critical thinking skills
- Practical and/or problem-solving skills
Class flow
In general, a 100 minutes exercise using an FPGA board will be conducted after two 100 minutes lectures.
Course schedule/Objectives
| Course schedule | Objectives | |
|---|---|---|
| Class 1 | Basic Structure of Computer Systems |
Understand the basic structure of computer systems. |
| Class 2 | Trends in Performance and Power |
Understand the trends in performance and power. |
| Class 3 | Computer Design Exercise(1) |
Computer Design Exercise(1) |
| Class 4 | Memory Technologies |
Understand memory technologies. |
| Class 5 | Computer Design Exercise(2) |
Computer Design Exercise(2) |
| Class 6 | Caches: Direct-Mapped |
Understand the direct-mapped caches. |
| Class 7 | Caches: Set-Associative |
Understand the set-associative caches. |
| Class 8 | Computer Design Exercise(3) |
Computer Design Exercise(3) |
| Class 9 | Memory Hierarchy and Dependability |
Understand memory hierarchy and dependability. |
| Class 10 | Pipelined Processor |
Understand pipelined processors. |
| Class 11 | Computer Design Exercise(4) |
Computer Design Exercise(4) |
| Class 12 | Superscalar Processor |
Understand superscalar processors. |
| Class 13 | Branch Prediction |
Understand branch prediction. |
| Class 14 | Computer Design Exercise(5) |
Computer Design Exercise(5) |
| Class 15 | Data-Level Parallelism in Vector and SIMD |
Understand the data-level parallelism in vector and SIMD. |
| Class 16 | Virtual Memory and Security |
Understand virtual memory and security issues. |
| Class 17 | Computer Design Exercise(6) |
Computer Design Exercise(6) |
| Class 18 | Input/Output and Bus |
Understand Input/Output and bus. |
| Class 19 | Interconnection Network |
Understand interconnection networks. |
| Class 20 | Computer Design Exercise(7) |
Computer Design Exercise(7) |
| Class 21 | Multiprocessors and Multicore |
Understand multiprocessors and multicore. |
Study advice (preparation and review)
To enhance effective learning, students are encouraged to spend a certain length of time outside of class on preparation and review (including for assignments), as specified by the Tokyo Institute of Technology Rules on Undergraduate Learning (東京工業大学学修規程) and the Tokyo Institute of Technology Rules on Graduate Learning (東京工業大学大学院学修規程), for each class.
They should do so by referring to textbooks and other course material.
Textbook(s)
David A. Patterson, John L. Hennessy. Computer Organization and Design RISC-V Edition: The Hardware/Software Interface. Morgan Kaufmann.
Reference books, course materials, etc.
None.
Evaluation methods and criteria
Students will be assessed on their understanding of computer architecture and the ability to apply them to implement small computer systems with a hardware description language (HDL).
Students' course scores are based on exercise problems (60%) and a final examination (40%).
Related courses
- CSC.T252 ： Switching Circuit Theory
- CSC.T262 ： Assembly Language
- CSC.T372 ： Compiler Construction
- CSC.T341 ： Computer Logic Design
- CSC.T433 ： Advanced Computer Architecture
Prerequisites
No prerequisites are necessary, but enrollment in the related course of Computer Logic Design is desirable.
Contact information (e-mail and phone) Notice : Please replace from ”[at]” to ”@”(half-width character).
Kise Kenji: kise[at]comp.isct.ac.jp
Office hours
Contact by e-mail in advance to schedule an appointment.